Room: Exhibit Hall | Forum 8
Purpose: To develop a cost-effective and compact electronics readout and processing system for a small animal PET scanner.
Methods: For the electronics readout system of our PET scanner, each detector module is read out by one Detector level (D-level) board. Data from D-level board are processed on the System level (S-level) board, such as data buffering and coincidence event selection. The latest Sigma-Delta Modulation (SDM) circuit was implemented for reading detector signals. D-level board includes front-end analog and digital boards. An FPGA evaluation board is used as our S-level board.
Results: Total 12 D-level boards are under construction and will be connected to all PET detectors using customized Flat Flex Cable (FFC). Each D-level board processes 64-ch charge-sensitive signals, with half are positive while the other half are negative polarity signals. There are total 768-ch charge-sensitive signals to be read out in the system. Processed single-event data on D-level board is sent to S-level board for coincidence-event selection via Low-Voltage Differential Signaling (LVDS) cable at a data rate of 400 Mbps. The maximum data rate on the S-level board is 4.8 Gbps. A PCIE Gen 2 is developed based on Altera FPGA, with tested data rate at about 8 Gbps, which is sufficient for the imaging data acquisition requirement. One PET detector module with the readout system shows a good performance in terms of flood source, energy resolution (~18%), timing resolution (~2.6 ns).
Conclusion: D-level electronics demonstrated its good performance for PET application. Full PET scanner readout electronics is partially tested with good projected performance.
Funding Support, Disclosures, and Conflict of Interest: The work was supported by 1R01EB019438, 1R01CA218402, R21 CA187717.